Lateral Power Semiconductor Device and Method for Manufacturing a Lateral Power Semiconductor Device

ABSTRACT

A lateral power semiconductor device includes a semiconductor body having a first surface and a second opposite surface, a first main electrode, a second main electrode, a plurality of switchable semiconductor cells and at least one curved semiconductor portion. The first main electrode includes at least two sections and is arranged on the first surface. The second main electrode is arranged on the first surface and between the two sections of the first main electrode. The plurality of switchable semiconductor cells is arranged between a respective one of the two sections of the first main electrode and the second main electrode and is configured to provide a controllable conductive path between the first main electrode and the second main electrode. The curved semiconductor portion is between the first main electrode and the second main electrode and has increasing doping concentration from the first main electrode to the second main electrode.

TECHNICAL FIELD

Embodiments described herein relate to lateral power semiconductordevices with improved avalanche and commutation characteristics, and tomethods for manufacturing a lateral power semiconductor device.

BACKGROUND

In comparison with vertical devices, lateral power semiconductor devicesare suitable for small and medium currents since they do not need anedge termination region that consumes additional chip area. Currently,lateral power semiconductor devices are designed to maximize the ratedtotal current for a given chip area. This may cause problems in regionswhere the electrical field is locally increased due to bending of theelectrical field lines.

In view of the above, there is a need for improvement.

SUMMARY

According to an embodiment, a lateral power semiconductor deviceincludes a semiconductor body having a first surface and a secondsurface opposite the first surface. A first main electrode having atleast two sections is arranged on the first surface, and a second mainelectrode is arranged on the first surface between the two sections ofthe first main electrode. A plurality of switchable semiconductor cellsis arranged between a respective one of the two sections of the firstmain electrode and the second main electrode and is configured toprovide a controllable conductive path between the first main electrodeand the second main electrode. At least one curved semiconductor portionis arranged between the first main electrode and the second mainelectrode with increasing doping concentration from the first mainelectrode to the second main electrode.

According to an embodiment, a lateral power semiconductor deviceincludes a semiconductor body having a first surface, a semiconductorsubstrate and a semiconductor layer on the semiconductor substrate, anda loop structure having, from a top view on the first surface, at leastone curved semiconductor portion and at least one straight semiconductorportion including a plurality of switchable semiconductor cells. Eachswitchable semiconductor cell includes a drift region formed in thesemiconductor layer, a drift control region formed in the semiconductorlayer adjacent to the drift region, and an accumulation dielectricelectrically insulating the drift region from the drift control region.Insulating layers electrically insulate the drift control region of eachswitchable semiconductor cell from the semiconductor substrate. Thecurved semiconductor portion is formed in the semiconductor layer, andcomprises an outer curved boundary partially surrounding an innerboundary from the top view on the first surface, wherein the dopingconcentration of the curved semiconductor portion increases from theouter curved boundary to the inner boundary.

According to an embodiment, a lateral power semiconductor deviceincludes a semiconductor body having a first surface, a first dopingregion of a first conductivity type, a second doping region of a secondconductivity type forming a pn-junction with the first doping region, athird doping region of the first conductivity type forming a mainpn-junction with the second doping region, and a fourth doping region incontact with the third doping region, wherein the main pn-junctionsurrounds the third doping region from a top view on the first surface.The third doping region surrounds the fourth doping region in top viewon the first surface. The third doping region includes straightsemiconductor portions and curved semiconductor portions from the topview on the first surface. The doping concentration of the curvedsemiconductor portions increases from the main pn-junction to the fourthdoping region.

According to an embodiment, a method for manufacturing a lateral powersemiconductor device includes providing a semiconductor body having asemiconductor substrate and a semiconductor layer on the semiconductorsubstrate, the semiconductor layer forming a first surface of thesemiconductor body; forming a loop structure in the first surfacehaving, from a top view, at least one curved semiconductor portion andat least one straight semiconductor portion having a plurality ofswitchable semiconductor cells, each switchable semiconductor cellhaving a drift region formed in the semiconductor layer, a drift controlregion formed in the semiconductor layer adjacent to the drift region,and an accumulation dielectric electrically insulating the drift regionfrom the drift control region; and forming insulating layers between thedrift control region and the semiconductor substrate to electricallyinsulate the drift control region of each switchable semiconductor cellfrom the semiconductor substrate; wherein the curved semiconductorportion is formed in the semiconductor layer and comprises an outercurved boundary and an inner boundary from the top view on the firstsurface, wherein the doping concentration of the curved semiconductorportion increases from the outer curved boundary to the inner boundary.

Those skilled in the art will recognize additional features andadvantages upon reading the following detailed description, and uponviewing the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The components in the figures are not necessarily to scale, insteademphasis being placed upon illustrating the principles of the invention.Moreover, in the figures, like reference numerals designatecorresponding parts. In the drawings:

FIG. 1 illustrates a top view on a lateral power semiconductor deviceaccording to an embodiment;

FIG. 2 illustrates an enlarged view of a portion of a lateral powersemiconductor device according to an embodiment;

FIG. 3 illustrates a vertical cross section through a curvedsemiconductor portion of a lateral power semiconductor device accordingto an embodiment;

FIGS. 4A and 4B illustrate electrical field distributions across regionsof the lateral power semiconductor device;

FIGS. 5A to 5D illustrate switchable semiconductor cells of a lateralpower semiconductor device according to an embodiment;

FIGS. 6A to 6D illustrate processes for manufacturing a lateral powersemiconductor device according to an embodiment;

FIG. 7 illustrates a process for manufacturing a lateral powersemiconductor device according to an embodiment;

FIG. 8 illustrates a process for manufacturing a lateral powersemiconductor device according to an embodiment; and

FIGS. 9A and 9B illustrate a process for manufacturing a lateral powersemiconductor device according to an embodiment.

DETAILED DESCRIPTION

In the following Detailed Description, reference is made to theaccompanying drawings, which form a part hereof, and in which are shownby way of illustration specific embodiments in which the invention maybe practised. In this regard, directional terminology, such as “top”,“bottom”, “front”, “back”, leading”, “trailing” etc., is used withreference to the orientation of the Figure(s) being described. Becausecomponents of embodiments can be positioned in a number of differentorientations, the directional terminology is used for purpose ofillustration and is in no way limiting. It is to be understood thatother embodiments may be utilised and structural or logical changes maybe made without departing from the scope of the present invention. Thefollowing detailed description, therefore, is not to be taken in alimiting sense, and the scope of the present invention is defined by theappended claims. The embodiments being described use specific language,which should not be construed as limiting the scope of the appendedclaims.

The term “lateral” as used in this specification intends to describe anorientation parallel to the main surface of a semiconductor substrate.

The term “vertical” as used in this specification intends to describe anorientation, which is arranged perpendicular to the main surface of thesemiconductor substrate.

In this specification, a second surface of a semiconductor substrate isconsidered to be formed by the lower or back-side surface while a firstsurface is considered to be formed by the upper, front or main surfaceof the semiconductor substrate. The terms “above” and “below” as used inthis specification therefore describe a relative location of astructural feature to another structural feature with consideration ofthis orientation.

The terms “electrical connection” and “electrically connected” describesan ohmic connection between two elements.

FIGS. 1-3 depict a lateral power semiconductor device according to anembodiment. FIG. 1 illustrates a top view on a first surface 111 (seeFIG. 3) of a semiconductor body 110 of the lateral power semiconductordevice. A first main electrode 131 and a second main electrode 132 arearranged on the first surface 111. The first main electrode 131 isdisposed from, and surrounds, the second main electrode 132.

The first electrode 131 includes at least two straight sections 131 aand 131 b arranged on the first surface 111. The second main electrode132 is arranged between the two straight sections 131 a and 131 b.

The first and second main electrodes 131, 132 are in electrical contactwith respective doping regions that are arranged below the first andsecond main electrodes 131, 132 that are not shown in FIG. 1. FIG. 2,illustrating an enlarged section of FIG. 1 without the first and secondmain electrodes 131, 132, shows a first semiconductor region 141 whichmay be, for example a source region. The first semiconductor region 141is of a first conductivity type, which may be, for example, n-type.

According to an embodiment, the first semiconductor region 141 may be atleast partially omitted at the outer curved boundary. FIG. 2 shows thefirst semiconductor region 141 including first sections 141 a formingstraight regions and second sections 141 b, in this case, forming curvedregions each of which connects respective two of the first sections 141a. The first sections 141 a can form the source regions of the cells ofthe lateral power semiconductor device. The second sections 141 b areoptional and do not need to be formed. The optional second sections 141b are marked by dashed lines. According to an embodiment and shown e.g.,in FIG. 5A, in a part of the straight regions, e.g. in a doping region126 as shown in FIG. 2 or at the end of drift control regions, the firstsemiconductor region 141 can be alternatively and/or additionally atleast partially omitted. These regions where the doping of thesemiconductor region 141 is omitted in the straight regions, for examplebetween adjacent regions 241 in FIG. 5A, can be understood as belongingto the second sections 141 b.

The first semiconductor region 141, when including the first and secondsections 141 a, 141 b, completely surrounds a fourth semiconductorregion 144, which may be of the first conductivity type to form a drainregion, for example. When the first semiconductor region 141 includesonly the first sections 141 a, the fourth semiconductor region 144 isdisposed between the first sections 141 a of the first semiconductorregion 141, as is the case when the first semiconductor region 141completely surrounds the fourth semiconductor region 144. The fourthsemiconductor region 144, which may form a drain region, is inelectrical contact with the second main electrode 132, which is drainmetallization in this embodiment. The first semiconductor region 141 isin electrical contact with the first main electrode 131, which is asource metallization in this embodiment.

Between the first main electrode 131 and the second main electrode 132there is a closed loop structure 120 on the first surface 111 thatincludes straight semiconductor portions 121 and curved semiconductorportions 122, as best shown in FIG. 1. The closed loop structure 120typically completely surrounds the fourth doping region 144.

The closed loop structure 120 is mainly formed by a third doping region143 which may be of the first conductivity type. In the presentembodiment, the third doping region 143 is weakly n-doped having adoping concentration that is less than the doping concentration of thefourth doping region 144. The third doping region 143 typically forms adrift region of the lateral power device. Adjacent to the third dopingregion 143 is a second doping region 142, of the second conductivitytype, i.e. of p-type, that forms a body region. A main pn-junction 145is formed between the second doping region 142 and the third dopingregion 143. The second doping region 142 is arranged between the firstdoping region 141, and the third doping region 143. The first doping 141region is arranged adjacent to the second doping region 142.

The main pn-junction 145 can be considered as forming an outer border orouter curved boundary of the closed loop structure 120, i.e., of thethird doping region 143. The second doping region 142 and first dopingregion 141, although shown in FIG. 2 to form ring structures followingthe contour of the main pn-junction 145, can have shapes deviating fromthe course of the main pn-junction 145, for example in the curvedsemiconductor portions 122.

According to an embodiment, the first doping region 141 and/or thesecond doping region 142 may be formed by individual doping islandsarranged substantially along the line of the main pn-junction 145 asshown in FIG. 2. In this case, the course of the main pn-junction 145can show some deviations compared to FIG. 2, e.g., can include somewave-kind line. According to an embodiment, one or more of the firstdoping region 141 and/or second doping region 142 can be connected tothe first main electrode 131.

For example, the third doping region 143 may be formed as a ringstructure having two main straight sections, corresponding to thestraight semiconductor portions 121, running parallel to each other andhaving the fourth doping region 144 disposed therebetween. Furthermore,the third doping region 143 may include two semi-ring sections thatcorrespond to the curved semiconductor portions 122 and connect thestraight sections so that the fourth doping region 144 is completelysurrounded by the third doping region 143. The second doping region 142may include two straight sections 121 between which the straightsections of the third doping region 143 are arranged. Along the outerboundary of the semi-ring sections 122 of the third doping region 143,islands of the second doping region 142 may be arranged. According tothis embodiment, continuous pn-junctions 145 are formed between thestraight sections 121 of the second doping region 142 and the thirddoping region 143. The pn-junction 145 along the outer boundary of thesemi-ring sections of the third doping region 143 includes respectivesections formed by a respective island of the second doped region 142and the semi-ring sections 122 of the third doping region 143. The spacebetween adjacent islands of the second doping regions 142 is such thatthis space is completely depleted in reverse mode of the power device.

When the second sections 141 b of the first doping region 141 arepresent, these sections 141 b can cause latching during commutation ofthe power device. To avoid latching, the second sections 141 b may beomitted. Furthermore, when the second sections 141 b of the first dopingregion 141 are present, a portion of the electron charge emanating fromthe fourth doping 144 forming a drain region is drained through thesecond sections 141 b, as the second sections 141 b form together withthe second doping region 142 and the third doping region annpn-transistor. In this case, the surplus of charges in the semi-ringsections 122 of the third doping region 143 is beneficially lowered. Ofthe above described two processes, the process that dominates depends onthe actual doping and/or geometrical relations. Thus, by appropriatelyselecting the doping relations and/or geometry of the structure,latching can be avoided even when the second sections 141 b are formedto reduce the surplus of charges.

A junction between the third doping region 143 and the fourth dopingregion 144, for example an nn+-junction, may be considered to form aninner boundary 147 of the closed loop structure 120.

The geometrical arrangement of the first doping region 141 and thefourth doping region 144 is not limited to the embodiment shown herein.For example, each of the first and fourth doping region 141, 144 mayhave, when viewed onto the first surface 111, a fin-like shape whereinthe fins of each doping region interdigitate with the fins of the otherdoping region. Irrespective of the actual geometry of the first dopingregion 141 and the second doping region 144, both regions remain spacedapart from each other with the closed loop structure 120 arrangedbetween the first and second doping region 141, 144.

The closed loop structure 120 includes a plurality of switchablesemiconductor cells 140 arranged in the straight semiconductor portions121 between the first semiconductor region 141 and the fourthsemiconductor region 144 as best shown in FIG. 2. The switchablesemiconductor cells 140 are therefore also arranged between the firstmain electrode 131 and the second main electrode 132. The switchablesemiconductor cells 140 provide a controllable conductive path betweenthe first main electrode 131 and the second main electrode 132 as willbe described further below.

As shown in FIG. 2, a doping region 126, which does not includeswitchable semiconductor cells, is arranged between the semiconductorcells 140 and the curved semiconductor portion 122 so that the curvedsemiconductor portion 122 is spaced from the semiconductor cells 140.The doping region 126 is part of the straight portion 121 in thisembodiment.

The curved semiconductor portion 122 has a doping concentrationincreasing from the first main electrode 131 to the second mainelectrode 132. This is illustrated in FIG. 2 by the dashed half-circleswith increased density towards the fourth doping region 144. The dopingconcentration of the curved semiconductor portion 122 can increase by afactor of about 1/R with R being the distance from an imaginarygeometrical center arranged in the fourth doping region 144. Accordingto an embodiment, the doping concentration in the curved semiconductorportion 122 may have a substantially stepwise characteristic with alower doped part 143 a and a higher doped part 143 a.

In the present embodiment, the closed loop structure 120 surrounding thefourth doping region 144 includes at least two curved semiconductorportions 122 and at least two straight semiconductor portions 121 whichcomprise a plurality of switchable semiconductor cells 140. The numberof the curved semiconductor portions 122 and the straight semiconductorportions 121 is, however, not limited to two and depends on the shape ofthe first and fourth doping region 141, 144. In case of fin-shaped firstand fourth doping regions 141, 144, the number of the curvedsemiconductor portions 122 and the straight semiconductor portions 121is larger than two. For example, when the fourth semiconductor region144 has a substantially square-like shape with rounded edges, the closedloop structure includes four curved semiconductor portions 122 and fourstraight semiconductor portions 121.

The geometrical shape of the closed loop structure 120 of the presentembodiment can be described as stadium having two straight semiconductorportions 121 which are arranged parallel to each other and which areconnected by the substantially semi-circular curved semiconductorportions 122. The fourth doping region 144 is a rather elongated regionwith rounded edges, one of which is shown in FIG. 2.

The course of the electrical field during blocking state is mainlydefined by the course of the main pn-junction 145, the outer shape ofthe fourth doping region 144, and the doping relation of the thirddoping region 143. Contrary to other approaches that place active cellsinto curved regions to maximize the total current of the lateralsemiconductor device during the on-state, the present embodiment doesnot include active semiconductor cells in the curved semiconductorportions 122.

During blocking operation, there is a large voltage difference betweenthe first doping region 141, or the second doping region 142 when thefirst doping region 141 does not include second sections 141 b, and thefourth doping region 144, since the semiconductor cells 140 are inblocking state and do not provide a conductive path between the firstdoping region 141 and the fourth doping region 144. The first and seconddoping regions 141, 142 can be on the same electrical potential whenboth are electrically connected to the first main electrode 131. Duringstatic blocking operation, the maximum of the electric field is locatedat the main pn junction 145. The field lines of the electrical fieldbetween the second doping region 142, the semiconductor substrate (notshown in FIG. 2) and the fourth doping region 144 arethree-dimensionally bent in the curved semiconductor regions 122. Thus,there is a local increase of the electrical field in the curvedsemiconductor regions 122 in comparison to the straight semiconductorregions 121. The shape and doping values of the third doping region 143and the fourth doping region 144 may be further used to increase theelectric field at the main pn-junction 145 in the curved semiconductorregions 122 in comparison to the straight semiconductor regions 121.Therefore, the value of the electric field when avalanche multiplicationstarts, is first reached in the curved semiconductor regions 122.

When avalanche occurs in the curved semiconductor region 122, forexample close to the second semiconductor region 142, charge carriersare generated and separated by the electrical field. Assume that thefourth doping region 144 is on a higher electrical potential than thefirst doping region 141 and second doping region 142 during blockingmode. The third doping region 143 forms a drift region and is weaklyn-doped. Since the absolute value of the electric field decreasesproportionally to the charge in the space charge area, the slope of thefield curve in the lower doped part 143 a of the third doping region 143is lesser as compared to the higher doped part 143 b. Free electrons aregenerated in the third doping region 143 by the avalanche effect andmove to the fourth doping region 144 on account of the prevailingelectrical field between the fourth doping region 144 and the seconddoping region 142. Due to the geometrical effect of the curvature, thelocal exaggeration of the current density and thus the electron densityis mainly close to the fourth doping region 144. This is beneficialparticularly when the fourth doping region 144 forms a drain region. Inthis case, the local exaggeration of the electrical field is remote fromthe main pn-junction 145. Thus, an increased amount of electrons towardsthe fourth doping region 144 partially compensate the positive netcharge of the donators in the n-doped third doping region 143 and fourthdoping region 144. The reduction of the positive net charge results in adeviation of the electrical field in comparison to the case in which nocurrent flows and an in which the electrical field distribution is onlydefined by the background doping distribution. These two cases areschematically illustrated in FIG. 4A, assuming a homogeneous electroncurrent density. Taking into account the increasing electron currentdensity and thus increasing negative charge density, the gradient of theelectric field approaching the fourth doped region 144 decreases in anon-linear way.

The vertical dashed line in FIG. 4A indicates the location of thejunction between the third doping region 143 and the fourth dopingregion 144. The solid line corresponds to the case where no current ofgenerated electrons flows, i.e., where the electrical field is definedby the background doping p only, which is assumed to be constant in eachof the respective doping regions 143 a, 143 b and which corresponds tothe doping concentration N_(D) ⁺ of the donators. Due to a partialcompensation by the electrons “accumulating” towards the junctionbetween the third doping region 143 a, 143 b, the background doping ispartially compensated so that the “effective” positive background dopingρ corresponds to the doping concentration N_(D) ⁺ of the donators plusthe concentration of the electrons. Note that the charge of electrons isnegative which leads to a reduction of ρ. The resulting electrical fielddistribution is indicated by the dashed line in FIG. 4A.

It should be noted here that the “accumulation” of electrons is adynamic process. The density of the electrons is higher close to thefourth doping region 144 because electrons, which are generated in agreater distance from junction between the third and fourth dopingregion 143, 144, flow towards this junction. In addition, thegeometrical effect of the bent electrical field causes the electrons toconcentrate towards the curved junction between the third and the fourthdoping region 143, 144. Hence, on average, the concentration ofelectrons is increased and remains increased during avalanche.

The reduced positive net charge results in a reduction of the slope ofthe electrical field as illustrated in FIG. 4A which shows that thegrad(E) is slightly reduced. As a consequence, the blocking voltageincreases. The maximum blocking voltage is provided when the electricalfiled is constant (grad(E)=constant). In this case, the counter chargefor the charge in the second doping region 142 is delivered in total bythe high donator density of the fourth doping region 144 and lead to analmost abrupt reduction of the electric field. The increased blockingvoltage in the curved semiconductor portion 122 in turn acts against theavalanche so that a self-stabilising effect is observed.

Assume that the current caused by avalanche increases. As a consequence,to maintain the blocking state, the voltage between the first and thefourth doping region 141, 144, which mainly drops over the third dopingregion 143, would also rise. This can lead to a situation where themaximum of the electrical field is close to or at the junction betweenthe third and the fourth doping region 143, 144. In this case, thecurrent-voltage-characteristics “snaps back,” which eventually leads toa destruction of the lateral device.

To prevent this and to allow higher avalanche currents withoutdestruction of the device, the background doping concentration of thecurved semiconductor portions 122 can be raised. Furthermore, a dopingconcentration increasing towards the fourth doping region 144 furtherimproves the avalanche robustness as an increasing doping concentrationat least partially compensates the geometrical factor of the curvedelectrical field lines in the curved semiconductor region 122. Forexample, the doping concentration in the third doping region 143 canincrease with 1/R with R being a distance from a geometrical center inthe fourth doping region 144 close to the junction between the fourthdoping region 144 and the third doping region 143.

According to a particular embodiment, the curved semiconductor portion122 can have an outer boundary which is mainly defined by the mainpn-junction 145. This outer boundary can be curved in general, forexample or can be semi-circular as shown in FIG. 2. With reducingdistance R from the geometrical center of this semi-circle, the dopingconcentration increases.

The curved semiconductor portion 122 can have an inner boundary definedby the junction between the third doping region 143 and the fourthdoping region 144. The inner boundary may be curved, for examplesemi-circular, as shown in FIG. 2. The increasing doping concentrationwithin the third doping region 143 may be adapted to follow the bendingradius of the inner boundary. In the case of a semi-circular innerboundary as shown in FIG. 2, the bending radius is constant. In othercases, the bending radius may increase or decrease. The increase of thedoping concentration in the third region 143 may then be adaptedaccordingly.

The increasing doping concentration results in an electric fielddistribution as indicated by the dashed line in FIG. 4B, which shows, ascomparison, the electrical field distribution for a constant backgrounddoping (solid line) at the same blocking voltage applied between thesecond doping region 142 and the fourth doping region 144. The blockingvoltage, i.e., the integral over the electric field strength, or inother words the onset of avalanche generation, can be reduced whenlocally increasing the background doping towards the junction betweenthe third doping region 143 and the fourth doping region 144.

For illustration purposes only, the background doping of lateral devicehaving a rated blocking voltage of 600 V is less than about1.4*10¹⁴/cm³. This doping concentration prevails also at the mainpn-junction 145 in the curved semiconductor portions 122. The dopingconcentration increases towards the junction between the third dopingregion 143 and the fourth doping region 144 to a value of about 10¹⁵ to10¹⁶/cm³. Typically, the doping concentration increases from the mainpn-junction 145 to the junction between the third doping region 143 andthe fourth doping region 144 by a factor of about 5 to 100.

On account of the increased background doping concentration in the thirddoping region 143 in the curved semiconductor portion 122, the maximumpermissible avalanche current increases. On the other hand, the blockingvoltage at which avalanche occurs reduces. This is beneficial since theavalanche breakdown will occur in the curved semiconductor portions 122and not in the switchable semiconductor cells 140. Furthermore, asdescribed above, since the avalanche in the curved semiconductor portion122 is self-stabilising, the lateral semiconductor device exhibits animproved avalanche robustness. The curved semiconductor portions 122 cantherefore be referred to as “avalanche regions”.

To ensure that the switchable semiconductor cells 140 forming the activeregion of the lateral semiconductor device, and the structures of thecells 140, for example oxide layers, are not influenced by the avalanchebreakdown, the region 126 is provided between the curved semiconductorportion 122 and the switchable semiconductor cells 140 in the straightportion 121 as shown in FIG. 2. The lateral width “a” of the region 126can be between about 5% to 100% of the distance in the straightsemiconductor portions 121 between the second semiconductor region 142and the fourth semiconductor region 144. The distance between the secondsemiconductor region 142 and the fourth semiconductor region 144 isdepending on the desired blocking capability of a lateral semiconductorswitch and may be estimated to be approximately 7.5 to 15 μm per 100V.For a device with a rated blocking voltage of 600V the distance betweenthe second semiconductor region 142 and the fourth semiconductor region144 should be in the range of about 45 μm to 90 μm and thus the value of“a” between about 2.25 μm and about 90 μm. The semiconductor region 126has a doping concentration that is less than the doping concentration inthe curved semiconductor portion 122 and can correspond to thebackground doping of the switchable semiconductor cells 140.

According to an embodiment, the peak doping concentration of thebackground doping within the third doping region 143 of the curvedsemiconductor portion 122 is spaced from the first surface 111, as shownin FIG. 3. FIG. 3 is a vertical cross section through the curvedsemiconductor portion 122 along the radius R shown in FIG. 2. In lateraldirection, i.e., from the main pn-junction 145 to the junction betweenthe third doping region 143 and the fourth doping region 144, the dopingconcentration increases, for example according to 1/R. The peak dopingconcentration for a given location X, however, is spaced from the firstsurface 111. The location of the peak doping concentration is indicatedby the dashed line.

Such a doping profile can be obtained by implantation with anappropriately selected implantation energy which implants the dopantsinto a given depth which will later corresponds to the location of thepeak doping concentration.

When the first main electrode 131 forms a source metallization and thesecond main electrode 132 a drain metallization, the outer rim of thelateral semiconductor device is at source potential while the center ofthe lateral semiconductor device is at drain potential. Control circuitsfor controlling the lateral semiconductor device can therefore beintegrated into the semiconductor body 110 without additional levelshifters. Furthermore, as shown in FIG. 3, the second doping regionforming a body region can be in electrical continuity with a p-dopedsubstrate 149 forming a lower part of the semiconductor body 110. Thisimproves electrical insulation of the lateral semiconductor device,facilitates integration, and ensures that the rim and the lower sideformed by a second surface 112 of the semiconductor body 110 is in thesame electrical potential. According to an embodiment and not shown inFIG. 3, the electrical contact between the p-doped substrate 149 and thesecond doping region 142 may be done without continuous doping as shownin FIG. 3 but with other means like bond wires, soldered clips or otherelectrical connections outside the semiconductor body 110.

In a particular embodiment, the third doping region 143 in the curvedsemiconductor portion 122 forms a pn-junction with the p-doped substrate149. This improves heat dissipation for the heat generated duringavalanche.

With respect to FIGS. 5A to 5D, the structure of the switchablesemiconductor cells 140 according to an embodiment is described. Theswitchable semiconductor cells 140 are so-called TEDFETs in thisembodiment and include two functional regions 200 and 300 as illustratedin FIG. 5A. Functional region 200 forms a “normal” FET while functionalregion 300 forms a drift control cell for forming and controlling anaccumulation channel in the FET.

The structure of the FET (functional region 200) is illustrated in FIG.5B showing a vertical section along line BB in FIG. 5A.

The FET cell is formed in a semiconductor body 210 including asemiconductor substrate 249 which may be, for example, p-doped and ann-doped semiconductor layer 248 formed on the semiconductor substrate249. Semiconductor layer 248 can be formed using e.g., epitaxial growth.The n-doping of the semiconductor layer 248 forms the background dopingof the switchable semiconductor cells 140. The semiconductor body 210has a first surface 211 and a second surface 212 opposite the firstsurface 211. The semiconductor layer 248 extends to the first surface211 and forms the third doping region 143 as described above, i.e.,forms a drift region 243. A p-doped region 242, which is part of thesecond doping region 142, is formed in the drift region 243. The p-dopedregion 242 functions as a body region and forms the main pn-junction 245with the drift region 243. A highly n-doped source region 241, beingpart of the first doping region 141, is embedded in the body region 242.A highly n-doped drain region 244, being part of the fourth dopingregion 144, is embedded in the drift region 243 and forms an nn+junction with the drift region 243. A source metallization 231, beingpart of the first main electrode 131, is in electrical contact withsource region 241 and the body region 241. Furthermore, a drainmetallization 232, being part of the second main electrode 132, is inelectrical contact with the drain region 244.

Above body region 242, and insulated therefrom by a gate dielectric 252,there is arranged a gate electrode 233 forming part of a third electrodeof the lateral power semiconductor device. The gate electrode 233 andthe drift region 243 are covered by a comparably thick insulation layer251 insulating the gate electrode 233 and the drift region 243 againstthe source metallization 231 and the drain metallization 232.

The p-doped body 242 and p-doped semiconductor substrate 249 can be inelectrical contact, for example by extending the body region 242 alongan outer edge or rim of the semiconductor body 210 as shown in FIG. 3.

It should be noted that FIGS. 5A to 5D only show the structure of theswitchable semiconductor cells 140 and not the complete device. The leftside in FIGS. 5A to 5D faces to the outer rim of the semiconductor body210 while the right side faces the center of the lateral semiconductordevice defined by the fourth doping region 144.

Adjacent to the FET cell 200, there is formed a drift control cell 300which is insulated from the FET cell 200 by an accumulation dielectric350 as best shown in FIGS. 5A and 5C with FIG. 5C being a cross sectionalong line CC in FIG. 5A.

The drift control cell 300 of the TEDFET is formed in the semiconductorbody 310 having the first surface 311, the second surface 312, thesemiconductor substrate 349, and the semiconductor layer 348 asdescribed above. However, distal to the FET cell 200, an insulatinglayer 353 is formed between the p-doped semiconductor substrate 349 andthe n-doped semiconductor layer 348. The semiconductor layer 348 can beformed using e.g., epitaxial growth. Together with the accumulationdielectric 350, the insulating layer 353 completely electricallyinsulates the drift control cell 300 from the adjacent FET cell 200 andthe semiconductor substrate 349. This is best shown in FIG. 5D showing athree-dimensional illustration of a switchable semiconductor cell 140including a FET cell 200 with an adjacent drift control cell 300.

The drift control cell 300 includes a p-doped first zone 342 and forminga main pn-junction 345 with a drift control region 343 formed by then-doped semiconductor layer 348. A highly n-doped second zone 344 isformed in the semiconductor layer 348 and forms an nn+-junction with thedrift control region 343. The first zone 342 is contacted by a firstterminal 331 while the second zone 344 is contacted by a second terminal332. The first terminal 331 can be electrically connected to the sourcemetallization 231 through a not shown diode element. Similarly, thesecond terminal 332 can be electrically to the drain metallization 232through a not shown diode.

According to an embodiment, the insulating layer 353 may also extendbelow the FET cell insulating the drift region 243 from the substrate212. According to a further embodiment, the insulating layer 353additionally or alternatively may also extend below the curvedsemiconductor portions 122 insulating the doping region 143 from thesubstrate 212. Insulating the drift region 243 and/or the doping region143 inhibits the injection of carriers into the substrate 212 duringoperation of the body diode and thus may further improve the dynamicbehaviour of the body diode. On the other hand, thermal performance isreduced due to the reduced heat flow through the insulating layer 353compared to a direct contact of semiconductor material.

A comparably thick insulating layer 351, which may be continuous withthe insulating layer 251, covers the drift control region 343 andprovides insulation against the first and the second terminals 331, 332,respectively.

Due to action of the drift control region 343, an accumulation channelis formed in the drift region 243 along the accumulation dielectric 350to reduce the on-state resistance in the conducting state of the lateralpower semiconductor device.

As shown in FIG. 5A, the switchable semiconductor cells 140 are arrangedadjacent to each other so that FET cells 200 and drift control cells 300are alternatingly arranged in the straight semiconductor portion 121 ofthe lateral power semiconductor device.

As described above, avalanche breakdown is confined or restricted to thecurved semiconductor portions 122 and, hence, does not influence theswitchable semiconductor cells 140 and particularly the accumulationdielectric 350. Therefore, trapping of hot charge carriers, which aregenerated during avalanche breakdown, in the accumulation dielectric 350can be significantly reduced. This effect is further improved when thepeak doping concentration of the third doping region 143 in the curvedsemiconductor portion 122 is spaced from the first surface 111 as inthis case the likelihood of hot carrier injected into the insulatinglayer 251, 351, which also covers the curved semiconductor portion 122,is also reduced.

The above described arrangement of the lateral power semiconductordevice further exhibits an improved commutating characteristic so thatthe lateral power semiconductor device has improved avalanche robustnessand an improved commutating characteristic.

During commutation, charge carriers stored in the device must be removedto bring the device into the blocking state. When the body-diode of theFET cells 200 is operating, as is the case for the structure shown inFIG. 5B, the drift region 243 is flooded with charge carriers. In theregion of the switchable semiconductor cells 140, a large portion of thecurrent is guided as channel current along the accumulation dielectric350. Furthermore, the body-diodes, when suitably dimensioned to be ableto handle large body diode currents, also causes the third doping region143, corresponding to the drift region 243, to be flooded with chargecarriers. When the device is now brought into the blocking state, thedoping concentration in the curved semiconductor portion 122 increasingtowards to the fourth doping region 144 acts as a field-stop regionpreventing the electrical field from quickly forwarding to the fourthdoping region 144 (drain region 244). Hence, the charge carriers remainfor a longer time in the third doping region 143 which leads to a moregentle commutation.

Furthermore, the current density for removing the positive chargecarriers (holes) is reduced by the geometrical effect of the curvedsemiconductor portion 122 as the hole current is towards the outerboundary of the curved semiconductor portion 122. This leads to a higherswitching robustness which is determined mainly by the hole currentdensity. Such behavior is beneficial for bridge circuits and resonantapplications, where the body diode can be subjected to hard commutationunder specific conditions which may lead to a destruction of the device.

The above described lateral power semiconductor device allows thesemiconductor body 110, i.e. the second side 112 of the semiconductorbody 110, to be at the source potential. Furthermore, driving circuitscan be easily integrated into the semiconductor body 110 laterallyoutside of the active regions of the power semiconductor device sincethe outer regions, as well as the backside of the semiconductor body110, are on the same electrical potential.

Alternatively, the fourth semiconductor region 144 can be on sourcepotential while the first and/or the second semiconductor region 141,142 can be on drain potential.

In a further aspect, a reverse blocking transistor can be integrated inthe regions of the switchable semiconductor cells 140, for example byforming an optional additional doping region 246 having a doping typeopposite to the doping type of the drain regions 244 and which iselectrically connected to the drain electrode 232 and isolates the drainregion 244 from the drift region 243. The electrical connection in FIG.5D is indicated by a line 247, but can be realized e.g., by a groovedcontact for the drain electrode 232 or by the additional doping region246 penetrating a part of the drain regions 244 reaching the firstsurface 211. Without applying a voltage to the drift control region 343,a lateral IGBT structure is thus provided that floods the drift region243 when the gate 233 is charged. This results in a reduction of thedrain voltage, and the voltage of the drift control region 343 is ableto generate a continuous channel formed as accumulation channel in thedrift region 243 and as inversion channel in the additional dopingregion 246. This modification improves the pulse current robustness ofthe lateral power semiconductor device. Furthermore, the reverseblocking capabilities are improved which drives the reverse current intothe curved semiconductor portions 122 of the third doping region 143having doping relations which are tailored, particularly due to theincreasing doping concentration, for optimal diode performance.Furthermore, active rectifier operation of the lateral powersemiconductor device is also possible by generating a conductive channelalong the accumulation dielectric 350 and increasing the voltage appliedto the gate electrode 233.

With reference to FIGS. 6A to 6D, a method for manufacturing a lateralpower semiconductor device is described.

A semiconductor body 410 having a semiconductor substrate 449 and asemiconductor layer 448 on the semiconductor substrate 449 is provided.The semiconductor layer 448 can be an epitaxially grown layer of adoping type opposite to the doping type of the semiconductor substrate449. In this case, the semiconductor layer 448 forms a pn-junction withthe semiconductor substrate 449. The semiconductor layer 448 can also beof the same doping type as the semiconductor substrate 449.

The semiconductor layer 448 extends to and forms a first surface 411 ofthe semiconductor body 410 as illustrated in FIG. 6A.

In a further process, a plurality of trenches 460 is formed in thesemiconductor layer 448. This is shown in the left part of FIG. 6A. Thetrenches 460 run along the regions where the drift control regions 343are formed in subsequent processes. For each drift control region 343, arespective trench 460 can be formed. The mesa regions between adjacenttrenches 460 form later the drift regions 243.

The trenches 460 can extend, in a top view as for example shown in FIG.2, from a region above the main pn-junction 145 to below the mainpn-junction 145 when referring to the orientation of FIG. 2. Thetrenches 460 therefore also extend through the region where later thefourth doping region 144 is formed. As shown in the embodiment of FIG.2, the trenches 460 may extend along the semiconductor cells 140 fromthe upper edge of the semiconductor body 110 to the lower edge of thesemiconductor body 110. As a plurality of lateral power semiconductordevices is formed on a wafer, the trenches 460 maybe formed to extend toregions which later form the edges of the lateral power semiconductordevices. Alternatively, the trenches 460 may extend to regions justoutside of the first semiconductor region 141.

In a further process, as illustrated in the left part of FIG. 6B, thesemiconductor body 410 is tempered at an elevated temperature in adeoxidizing atmosphere to cause surface migration of the semiconductormaterial of the semiconductor layer 448 until the trenches 460 arecovered by the semiconductor material to form respective cavities 461that are laterally spaced apart from each other. Since the “reflow” ofthe semiconductor material results in a mono-crystalline material, theextension of the trenches into other regions than the regions, where thedrift control regions are formed, is uncritical.

As an illustrative example, the trenches 460 can have a lateral width ofabout 300 nm to about 3000 nm and a length of about 30 μm to about 120μm for a device with 600V blocking capability. The minimal length of thetrenches can correspond with the length I_(T) of the lateral transistorcell which is connected to the desired blocking voltage V_(B) of thelateral transistor. In an embodiment, the I_(T) in μm is about 5 . . .20*V_(B)/100V. However the trenches can be much longer than these valuesand can be formed reaching through one or more chips or even through thewhole wafer. The above width changes in the tempering process and theinitial width of the trenches 460 should be adapted to allow for thischange. The pitch of the trenches 460 can be in the range of severalhundred nm which reliably prevents that adjacent trenches 460 mergeduring the tempering process. The depth of the trenches 460 can be inthe range of several μm. These dimensions are only illustrative and notlimiting.

The process conditions during tempering can be adjusted according tospecific needs. For illustration purposes, the temperature can be in arange from about 1000° C. to about 1150° C. when the semiconductor layer448 is a silicon semiconductor. In this temperature range, thesemiconductor material of the semiconductor layer 448 begins to “flow”and the trenches 460 start to get closed by the flowing material. On theother hand, the trenches 460 widen in their lower parts due to theflowing material. The trenches 460, however, are spaced apart from eachother by a lateral distance which is sufficient that the wideningtrenches 460 in their lower parts do not merge.

The tempering can be carried out, according to an embodiment, in adeoxidizing atmosphere, for example in a hydrogen atmosphere at lowpressure, for example at about 10 Torr (about 1.3·10³ Pa). The durationof the tempering process can be varied and can be selected in view ofthe temperature. A typical tempering time at the desired temperingtemperature is about 10 min.

In a further process, as illustrated in the left part of FIG. 6C, avertical channel 462 is formed extending from the first surface 411 toprovide an access to the cavities 461. According to an embodiment, onerespective channel 462 can be formed to extend to one respective cavity461. According to another embodiment, one channel 462 can provide accessto two or more cavities 461.

The cavities 461, which assume the shape of hollow pipes in the leftpart of FIG. 6C, have internal surfaces. In a further process, asillustrated in the left part of FIG. 6D, the internal surfaces of thecavities 461 are oxidized to form respective insulating layers 470,which later form the insulating layers 353. The channels 462 provide theaccess for the oxidising atmosphere to diffuse into the cavities 461.

The channels 462 are typically formed in regions outside the activeregion of the power semiconductor device. For example, the channels 462can be formed in the regions of the kerf or sawing frame along which thesemiconductor body 410 is finally cut to separate the powersemiconductor devices from each other.

The left parts of FIGS. 6A to 6D illustrate the formation of separateinsulating layers 470, which are only formed in the regions below thedrift control regions 343. In this case, the mesa regions between thetrenches 460 remain in contact with the semiconductor substrate 449. Forexample, the trenches 460 may be formed to extend as far as thesemiconductor substrate 449 so that the respective insulating layers 470are formed in the interface region between the semiconductor substrate449 and the semiconductor layer or semiconductor layer 448. The mesaregions that later form the drift regions can form respectivepn-junctions with the semiconductor substrate 449. These pn-junctionsinsulate the drift regions from the semiconductor substrate 449.

Leaving the drift regions in contact with the semiconductor substrate449 is beneficial for heat transfer from the lateral transistor cells toa heat sink, which is typically connected to the back side of thesemiconductor substrate 449, as the semiconductor material of the driftregions (mesa regions) in continuous with the semiconductor substrate449. To further improve heat transfer, the trenches 460 may only beformed in regions of the later straight semiconductor portions 121. Inother regions such as the curved semiconductor portions 122 and, forexample, below the fourth semiconductor region 144, no trenches 460 areformed so that the semiconductor material also remains continuous inthese regions and portions, respectively.

In addition to improved heat transfer, the cavities 261, which remainhollow even after formation of the insulating layer 471, reduce thecapacitive coupling of the drift control region 343 with thesemiconductor substrate 449.

In a further embodiment, as illustrated in the right parts of the FIGS.6A to 6D, a common insulating layer 471 is formed below the driftcontrol regions 343 and the drift regions 243. A plurality of closelyspaced trenches 465 is formed in the semiconductor layer 448. Whether atrench transforms to a single cavity or adjacent trenches merge to acommon cavity depends on the lateral spacing, i.e. pitch, of thetrenches. When arranging a plurality of closely spaced trenches 465 inan array, a cavity 466 is formed that has, in top view, the2-dimensional extension of the array. The cavity 466 may have a planeshape as illustrated in FIG. 6B. For example, a rectangular array ofclosely spaced trenches 465 form a substantially rectangular cavity 466with rounded corners (seen in top view) while a row of closely spacedtrenches 465 forms a substantially elongated cavity. Therefore, byselecting the arrangement of the trenches 108, virtually any cavityarrangement and shape can be formed.

In further processes, as illustrated in the right parts of the FIGS. 6Cand 6D, a vertical channel 467 is formed to provide access for anoxidising atmosphere to the cavity 466 to form an insulating layer 471on the internal surfaces of the cavity 466. The channel 467 is typicallyformed in regions outside the active region of the power semiconductordevice and can be sited arbitrarily in the region of the cavity 466. Forexample, the channel 467 can be formed in the regions of the kerf orsawing frame along which the semiconductor body 410 is finally cut toseparate the power semiconductor devices from each other. Heat transferfrom the lateral transistor to the heat sink is impaired by using acavity also underneath the drift regions 243. However, the capacitivecoupling between the drift regions 243 and the substrate 449 is reduced.

According to an embodiment, a compromise between thermal performance andcapacitive coupling of the lateral transistor may be done by combiningtubular cavities 461 only under the drift control regions 300, e.g., inan area closer to the source regions of the lateral device, and a twodimensional cavity 466 under both drift regions 200 and drift controlregions 300, e.g., in an area closer to drain regions. In this case, thenumber of channels 462, 467 may be reduced down to one channel in total.

By placing the cavity 466 under the curved semiconductor regions it canbe avoided that electrons or holes generated in diode operation of thelateral power semiconductor device or during avalanche can reach thesemiconductor substrate and thus can reach other portions of the device.

In further processes, a plurality of switchable semiconductor cells 140is formed as illustrated in FIGS. 5A to 5D. Each switchablesemiconductor cell 140 includes a drift region 243 formed in thesemiconductor layer 448, particularly in the mesa regions between theregions where the trenches 460 were formed. The drift control regions343 are formed in the semiconductor layer 448 adjacent to the driftregion 243 and above the insulating layers 470. The accumulationdielectrics 350 are formed between the drift region 243 and the driftcontrol region 343, for example by etching thin trenches. The etchingstops on the insulating layer 470. The thin trenches are subsequentlyfilled with an insulating material.

The semiconductor cells 140 form a straight semiconductor portion 121 ofthe loop structure 120 having, in top view on the first surface, atleast one curved semiconductor portion 122 and at least one straightsemiconductor portion 121.

In a further process, the curved semiconductor portion 122 is doped sothat the doping concentration of the curved semiconductor portion 122increases from the outer curved boundary 145 to the inner boundary 147.This can be, for example, done using one or several implantation masks.To reduce the number of process steps, the doping of the curvedsemiconductor portion 122 can be done with ion implantation throughwindows of a mask and a subsequent annealing step to reach diffusion ofthe dopant. The maximum doping concentration can be reached withoutmasking the ion implantation which can be done e.g., close to the innerboundary 147. On the way to the outer curved boundary 145, the densityof the windows in the mask is reduced thus reducing the mean amount ofdoping atoms implanted into the semiconductor material per area. Theminimum doping concentration can be reached by completely blocking theion implantation, i.e., without opening windows in the mask. Thisprocess can be repeated one or more times. From the position ofintegration it is desirable to use ion implantation steps and maskingsteps which are anyway needed in the production of the semiconductorchip.

An example is given in FIG. 8, which shows an implantation mask 880having a plurality of windows 881 and 882. The dashed lines in FIG. 8indicate the location of the outer boundary 145 and the inner boundary147 of the curved portions 122 formed by portions of the third dopingregion 143. The number, size and shape of the windows 881 may vary, forexample in radial direction while keeping the density constant incircumferential direction for a given radius. An inner window 882 can beformed as a semi-circular ring. By varying at least one of the number,size and shape of the windows 881, the implantation density can belocally adjusted. With a subsequent annealing step, the implanteddopants diffuse to smooth the implantation pattern defined by the mask880. When using small-sized windows, the local variation of theresulting doping can be even better controlled and the duration and/ortemperature of the subsequent annealing step can be reduced.

According to another embodiment, as illustrated in FIGS. 9A and 9B, afirst mask 901 is provided covering an outer region of the curvedsemiconductor portion 122, for example region 143 a shown in FIG. 2, andleaving an inner region of the curved semiconductor portion 122, forexample region 143 b, unmasked. The first mask 901 includes the firstwindow 981. Dopants are implanted using the first mask 901 as dopingmask. Then, a second mask 902 having a second window 982 is formed. Thesecond window 982 leaves a portion of the outer region adjoining theinner region unmasked. According to an embodiment, the size of thesecond window 982 can be larger than the size of the first window 981and extends further to the outer curved boundary 145. The second mask902 is used as implantation mask during a further implantation process.Hence, by increasing the size of the second window 982 relative to thefirst window 981 towards the outer curved boundary 145, the total amountof dopants that are implanted into the curved semiconductor portion 122is larger towards the inner boundary 147 than towards the outer boundary145.

By using the first and second mask 901, 902, at least a two-step dopingprofile from the inner boundary 147 to the outer curved boundary 145 canbe obtained. When using more than two masks, the number of steps in thedoping profile may be increased.

The first and second masks 901, 902 may be portions of implantationmasks which are used in other regions to form other doping regions suchas the fourth doping region 144, an optional field-stop layer, or thefirst doping region 141. Hence, by appropriately combining implantationsteps, the number of lithographic steps can be kept as small aspossible.

According to several embodiments, the mask windows 881, 882, 981 and 982shown in FIG. 8, FIGS. 9A and 9B can be permutated in all combinations.As an example windows like e.g., 881 may be used also in the first mask901 and/or the second mask 902 additionally or alternatively to a biggerwindow 981, 982. The second mask 902 and the first mask 901 can haveoverlapping windows like window 981 and window 982 shown in FIGS. 9A and9B. However, the window of the second mask 902 may be located only overmasked areas of the first mask 901. Of course, more than two masks canbe used.

With reference to FIG. 7, a further embodiment for manufacturing alateral power semiconductor device is described. In this embodiment, thedrift regions and the drift control regions are formed in a membrane ofthe semiconductor body 410. The insulation to the backside can beprovided by a hollow recess and/or an insulating layer formed in therecess. This avoids, in diode operation of the lateral powersemiconductor device, the electron-hole pairs generated during avalanchefrom reaching the semiconductor substrate and reaching other portions ofthe device.

As illustrated in FIG. 7, a recess 480 is formed, for example etched, inthe second surface 412 of the semiconductor body 410. The recess 480extends bottom regions of the drift control regions 343 and the driftregions 243.

In a further process, an insulating layer 471 may be formed on exposedsurface of the recess 480. The remaining space of the recess can be leftunfilled or can be filled by a material, such as a semiconductormaterial or an insulator like e.g., ceramics or a polymer which mayinclude other particles, even metal, which improves heat dissipation.When leaving the recess 480 unfilled, the empty recess provides theinsulation even without any extra insulating layer. Hence, the emptyrecess 480 can form an insulating layer.

As shown in FIG. 7, the insulating layer 471 and/or the recess 480insulates the drift regions 243 and the drift control regions 343 fromany further material which can later be formed on the second side 412 ofthe semiconductor body 410.

Spatially relative terms such as “under”, “below”, “lower”, “over”,“upper” and the like, are used for ease of description to explain thepositioning of one element relative to a second element. These terms areintended to encompass different orientations of the device in additionto different orientations than those depicted in the figures. Further,terms such as “first”, “second”, and the like, are also used to describevarious elements, regions, sections, etc. and are also not intended tobe limiting. Like terms refer to like elements throughout thedescription.

As used herein, the terms “having,” “containing,” “including,”“comprising” and the like are open ended terms that indicate thepresence of stated elements or features, but do not preclude additionalelements or features. The articles “a,” “an” and “the” are intended toinclude the plural as well as the singular, unless the context clearlyindicates otherwise.

With the above range of variations and applications in mind, it shouldbe understood that the present invention is not limited by the foregoingdescription, nor is it limited by the accompanying drawings. Instead,the present invention is limited only by the following claims and theirlegal equivalents.

What is claimed is:
 1. A lateral power semiconductor device, comprising:a semiconductor body having a first surface and a second surfaceopposite the first surface; a first main electrode comprising at leasttwo sections arranged on the first surface; a second main electrodearranged on the first surface and between the two sections of the firstmain electrode; a plurality of switchable semiconductor cells arrangedbetween a respective one of the two sections of the first main electrodeand the second main electrode and configured to provide a controllableconductive path between the first main electrode and the second mainelectrode; and at least one curved semiconductor portion between thefirst main electrode and the second main electrode with increasingdoping concentration from the first main electrode to the second mainelectrode.
 2. The lateral power semiconductor device according to claim1, wherein, in a cross-section perpendicular to the first surface, forany location in the curved semiconductor portion between the first mainelectrode and the second main electrode, a peak in the dopingconcentration is away from the first surface.
 3. The lateral powersemiconductor device according to claim 1, wherein the curvedsemiconductor portion and the plurality of switchable semiconductorcells form a closed loop structure surrounding the second mainelectrode.
 4. The lateral power semiconductor device according to claim3, wherein the closed loop structure comprises at least two curvedsemiconductor portions and at least two straight semiconductor portions,each of the straight semiconductor portions comprising a plurality ofswitchable semiconductor cells.
 5. The lateral power semiconductordevice according to claim 1, further comprising a doping region having adoping concentration lower than the doping concentration of the curvedsemiconductor portion, the doping region arranged between the curvedsemiconductor portion and the plurality of switchable semiconductorcells.
 6. The lateral power semiconductor device according to claim 1,wherein each switchable semiconductor cell comprises a drift region, adrift control region adjacent to the drift region, and an accumulationdielectric between the drift region and the drift control region.
 7. Thelateral power semiconductor device according to claim 6, wherein thesemiconductor body comprises a semiconductor substrate of oneconductivity type and a semiconductor layer of an opposite conductivitytype on and in contact with the semiconductor substrate, wherein thedrift control region of each switchable semiconductor cells is formed inthe semiconductor layer and is electrically insulated from thesemiconductor substrate by a respective insulating layer.
 8. The lateralpower semiconductor device according to claim 7, wherein the driftregion of each switchable semiconductor cell is formed in thesemiconductor layer and forms a pn-junction with the semiconductorsubstrate.
 9. The lateral power semiconductor device according to claim6, wherein the semiconductor body comprises a semiconductor substrate, asemiconductor layer on the semiconductor substrate, and an insulatinglayer at least between sections of the semiconductor substrate and thesemiconductor layer, and wherein the drift control region of eachswitchable semiconductor cells is formed in the semiconductor layer andis electrically insulated from the semiconductor substrate by theinsulating layer.
 10. The lateral power semiconductor device accordingto claim 1, wherein each switchable semiconductor cell comprises a drainregion in electrical contact with the second main electrode.
 11. Thelateral power semiconductor device according to claim 1, wherein eachswitchable semiconductor cell comprises a source region in electricalcontact with the first main electrode.
 12. The lateral powersemiconductor device according to claim 1, further comprising a fourthdoping region in electrical contact with the second main electrode, athird doping region of a first conductivity type surrounding the fourthdoping region and forming a junction with the fourth doping region, asecond doping region of a second conductivity type surrounding the thirddoping region and forming a main pn-junction with the third dopingregion, and a first doping region of the first conductivity type inelectrical contact with the first main electrode.
 13. The lateral powersemiconductor device according to claim 12, wherein the curvedsemiconductor portion is formed by a portion of the third doping regionand has, from a top view on the first surface, a curved outer boundarydefined by the main pn-junction and an inner curved boundary defined bythe junction between the third doping region and the fourth dopingregion, and wherein the doping concentration of the curved semiconductorportion increases from the outer boundary to the inner boundary by about1/R, wherein R is the distance from a center point arranged in thefourth doping region.
 14. A lateral power semiconductor device,comprising: a semiconductor body comprising a first surface, asemiconductor substrate and a semiconductor layer on the semiconductorsubstrate; a loop structure comprising, from a top view on the firstsurface, at least one curved semiconductor portion and at least onestraight semiconductor portion comprising a plurality of switchablesemiconductor cells, each switchable semiconductor cell comprising adrift region formed in the semiconductor layer, a drift control regionformed in the semiconductor layer adjacent to the drift region, and anaccumulation dielectric electrically insulating the drift region fromthe drift control region; and insulating layers electrically insulatingthe drift control region of each switchable semiconductor cell from thesemiconductor substrate; and wherein the curved semiconductor portion isformed in the semiconductor layer, and comprises an outer curvedboundary partially surrounding an inner boundary from the top view onthe first surface, and wherein the doping concentration of the curvedsemiconductor portion increases from the outer curved boundary to theinner boundary.
 15. The lateral power semiconductor device according toclaim 14, wherein the curved semiconductor portion forms a pn-junctionwith the semiconductor substrate.
 16. The lateral power semiconductordevice according to claim 14, further comprising a main pn-junctionsurrounding the loop structure from the top view on the first surface.17. The lateral power semiconductor device according to claim 14,wherein, in a cross-sectional view perpendicular to the first surface,for a given location in the curved semiconductor portion between theouter curved boundary and the inner boundary of the curved semiconductorportion, a peak in the doping concentration is away from from the firstsurface.
 18. A lateral power semiconductor device, comprising: asemiconductor body comprising a first surface; a first doping region ofa first conductivity type, a second doping region of a secondconductivity type forming a pn-junction with the first doping region, athird doping region of the first conductivity type forming a mainpn-junction with the second doping region, and a fourth doping region incontact with the third doping region; the main pn-junction surroundingthe third doping region from a top view on the first surface; the thirddoping region surrounding the fourth doping region from the top view onthe first surface; and the third doping region comprising straightsemiconductor portions and curved semiconductor portions from the topview on the first surface, wherein the doping concentration of thecurved semiconductor portions increases from the main pn-junction to thefourth doping region.
 19. The lateral power semiconductor deviceaccording to claim 18, further comprising a doping region and aplurality of switchable semiconductor cells arranged in the straightportions of the third doping region, the doping regions having a dopingconcentration lower than the doping concentration of the curvedsemiconductor portion and arranged between the curved semiconductorportion and the switchable semiconductor cells.
 20. The lateral powersemiconductor device according to claim 18, wherein the dopingconcentration of the curved semiconductor portion increases, at least insections, from the main pn-junction to the fourth doping region by about1/R, wherein R is a distance from a center point arranged in the fourthdoping region.
 21. A method for manufacturing a lateral powersemiconductor device, comprising: providing a semiconductor bodycomprising a semiconductor substrate and a semiconductor layer on thesemiconductor substrate, the semiconductor layer forming a first surfaceof the semiconductor body; forming a loop structure in the firstsurface, comprising, from a top view on the first surface, at least onecurved semiconductor portion and at least one straight semiconductorportion comprising a plurality of switchable semiconductor cells, eachswitchable semiconductor cell comprising a drift region formed in thesemiconductor layer, a drift control region formed in the semiconductorlayer adjacent to the drift region, and an accumulation dielectricelectrically insulating the drift region from the drift control region;and forming insulating layers between the drift control region and thesemiconductor substrate to electrically insulate the drift controlregion of each switchable semiconductor cell from the semiconductorsubstrate; wherein the curved semiconductor portion is formed in thesemiconductor layer and comprises an outer curved boundary and an innerboundary from the top view on the first surface, and wherein the dopingconcentration of the curved semiconductor portion increases from theouter curved boundary to the inner boundary.
 22. The method of claim 21,wherein the semiconductor layer is an epitaxial layer, and whereinforming the insulating layers comprises: forming a plurality of trenchesin the epitaxial layer; tempering the semiconductor body at an elevatedtemperature in a deoxidizing atmosphere to cause surface migration ofsemiconductor material of the epitaxial layer until the trenches arecovered by the semiconductor material to form respective cavities thatare laterally spaced apart from each other and that comprise surfaces;oxidizing the surfaces of the cavities to form the insulating layers.23. The method of claim 21, wherein the semiconductor layer is anepitaxial layer, and wherein a common insulating layer is formed betweenthe drift region and the semiconductor substrate and between the driftcontrol region and the semiconductor substrate, the method furthercomprising: forming a plurality of closely spaced trenches in theepitaxial layer; tempering the semiconductor body at an elevatedtemperature in a deoxidizing atmosphere to cause surface migration ofsemiconductor material of the epitaxial layer until the closely spacedtrenches coalesce to a single cavity that is covered by thesemiconductor material of the epitaxial layer; oxidizing a surface ofthe single cavity to form the insulating layers.
 24. The method of claim21, wherein forming the insulating layers comprises: forming a recess ina second surface of the semiconductor body which recess extends up tothe drift control regions and the drift regions.
 25. The method of claim24, further comprising forming an insulating layer in the recess. 26.The method of claim 21, wherein forming the curved semiconductor portioncomprises: providing a mask comprising a plurality of windows on thefirst surface of the semiconductor body, at least one of a size, number,and shape of the plurality of windows varying from the inner boundary tothe outer curved boundary; implanting dopants into the semiconductorlayer; and annealing the semiconductor layer to diffuse the implanteddopants.
 27. The method of claim 21, wherein forming the curvedsemiconductor portion comprises: providing a first mask having a firstwindow leaving an inner portion of the curved semiconductor portionadjacent to the inner boundary unmasked; implanting dopants using thefirst mask as an implantation mask; providing a second mask having asecond window that extends more to the outer boundary of the curvedsemiconductor portion relative to the first window of the first mask,the second mask leaving a further portion of the curved semiconductorportion adjacent to the inner portion of the curved semiconductorportion unmasked; implanting dopants using the second mask as animplantation mask; annealing the semiconductor layer to diffuse theimplanted dopants.